SLA24C01-SSLASHP datasheet(9/27 Pages) SIEMENS

9 / 27 page

SLx 24C01/02/P

Semiconductor Group

1998-07-27

Device Addressing and EEPROM Addressing

After a START condition, the master always transmits a Command Byte CSW or CSR.

After the acknowledge of the EEPROM a Control Byte follows, its content and the

transmitter depend on the previous Command Byte. The description of the Command

and Control Bytes is shown in table 2.

The device has an internal address counter which points to the current EEPROM

address.

The address counter is incremented

– after a data byte to be written has been acknowledged, during entry of further data

byte

– during a byte read, thus the address counter points to the following address after

reading a data byte.

Command Byte

Selects operation: the least significant bit b0 is low for a write

operation (Chip Select Write Command Byte CSW) or set high for a

read operation (Chip Select Read Command Byte CSR). In both

Command Bytes, the bit positions b3 to b1 are left undefined.

Control Byte

Following CSW (b0 = 0): contains the seven or eight lower bits of

the EEPROM address (EEA) bit A6 or A7 to A0, or an additional

command byte for the handling of the protection bit.

Following CSR (b0 = 1): contains the data read out, transmitted by

the EEPROM. The EEPROM data are read as long as the master

pulls down SDA after each byte in order to acknowledge the

transfer. The read operation is stopped by the master by releasing

SDA (no acknowledge is applied) followed by a STOP condition.

Table 2

Command and Control Byte for I

2C-Bus Addressing of Chip and EEPROM

Definition

Function

CSW

Chip Select for Write

CSR

Chip Select for Read

EEA

EEPROM address

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