SLA24C01-SSLASHP datasheet(12/27 Pages) SIEMENS

12 / 27 page

SLx 24C01/02/P

Semiconductor Group

1998-07-27

5.2

Page Write

Those bytes of the page that have not been addressed are not included in the

programming.

Figure 8

Page Write Sequence

The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for

speed enhancement in order to indicate the end of the erase/write cycle (refer to

chapter 5.3 Acknowledge Polling).

Address Setting

Thepagewrite procedureisthe same as thebytewrite

procedure up to the first data byte. In a page write instruction

however, entry of the EEPROM address byte EEA is followed

by a sequence of one to maximum eight data bytes with the

new data to be programmed. These bytes are transferred to

the internal page buffer of the EEPROM.

Transmission of Data

The first entered data byte will be stored according to the

EEPROM address n given by EEA (A0 to A6 or A7). The

internal address counter is incremented automatically after the

entered data byte has been acknowledged. The next data byte

is then stored at the next higher EEPROM address. EEPROM

addresses within the same page have common page address

bits A2 through A6 or A7. Only the respective three least

significant address bits A0 through A2 are incremented, as all

data bytes to be programmed simultaneously have to be

within the same page.

Programming Cycle

The master stops data entry by applying a STOP condition,

which also starts the internally timed erase/write cycle. In the

first step, all selected bytes are erased to “1”. With the next

internal step, the addressed bytes are written according to the

contents of the page buffer.

Command Byte

CSW

EEPROM Address

EEA n

Data Byte n

Data Byte n+1

Data Byte n+7

Bus Activity

Master

SDA Line

Bus Activity

EEPROM

IED02280

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