AFS090 datasheet(77/334 Pages) MICROSEMI

77 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 61

The following signals are used to configure the RAM4K9 memory element:

WIDTHA and WIDTHB

These signals enable the RAM to be configured in one of four allowable aspect ratios (Table 2-27).

BLKA and BLKB

These signals are active low and will enable the respective ports when asserted. When a BLKx signal is

deasserted, the corresponding port’s outputs hold the previous value.

WENA and WENB

These signals switch the RAM between read and write mode for the respective ports. A Low on these

signals indicates a write operation, and a High indicates a read.

CLKA and CLKB

These are the clock signals for the synchronous read and write operations. These can be driven

independently or with the same driver.

PIPEA and PIPEB

These signals are used to specify pipelined read on the output. A Low on PIPEA or PIPEB indicates a

nonpipelined read, and the data appears on the corresponding output in the same clock cycle. A High

indicates a pipelined, read and data appears on the corresponding output in the next clock cycle.

WMODEA and WMODEB

These signals are used to configure the behavior of the output when the RAM is in write mode. A Low on

these signals makes the output retain data from the previous read. A High indicates pass-through

behavior, wherein the data being written will appear immediately on the output. This signal is overridden

when the RAM is being read.

RESET

This active low signal resets the output to zero, disables reads and writes from the SRAM block, and

clears the data hold registers when asserted. It does not reset the contents of the memory.

ADDRA and ADDRB

These are used as read or write addresses, and they are 12 bits wide. When a depth of less than 4 k is

specified, the unused high-order bits must be grounded (Table 2-28).

Table 2-27 • Allowable Aspect Ratio Settings for WIDTHA[1:0]

WIDTHA1, WIDTHA0

WIDTHB1, WIDTHB0

D×W

4k×1

2k×2

1k×4

512×9

Note:

The aspect ratio settings are constant and cannot be changed on the fly.

Table 2-28 • Address Pins Unused/Used for Various Supported Bus Widths

D×W

ADDRx

Unused

Used

4k×1

None

[11:0]

2k×2

[11]

[10:0]

1k×4

[11:10]

[9:0]

512×9

[11:9]

[8:0]

Note:

The "x" in ADDRx implies A or B.

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