AFS090 datasheet(54/334 Pages) MICROSEMI

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Device Architecture

2- 38

R e visio n 2

Table 2-17 • VRPSM Signal Descriptions

Signal Name

Width Dir.

Function

VRPU

In Voltage Regulator Power-Up

0 – Voltage regulator disabled. PUB must be floated or pulled up, and

the TRST pin must be grounded to disable the voltage regulator.

1 – Voltage regulator enabled

VRINITSTATE

In Voltage Regulator Initial State

Defines the voltage Regulator status upon power-up of the 3.3 V. The

signal is configured by Libero IDE when the VRPSM macro is generated.

Tie off to 1 – Voltage regulator enables when 3.3 V is powered.

Tie off to 0 – Voltage regulator disables when 3.3 V is powered.

RTCPSMMATCH

In RTC Power System Management Match

Connect from RTCPSMATCH signal from RTC in AB

0 transition to 1 turns on the voltage regulator

PUB

In External pin, built-in weak pull-up

Power-Up Bar

0 – Enables voltage regulator at all times

TRST*

In External pin, JTAG Test Reset

1 – Enables voltage regulator at all times

FPGAGOOD

Out Indicator that the FPGA is powered and functional

No need to connect if it is not used.

1 – Indicates that the FPGA is powered up and functional.

0 – Not possible to read by FPGA since it has already powered off.

PUCORE

Out Power-Up Core

Inverted signal of PUB. No need to connect if it is not used.

VREN*

Out Voltage Regulator Enable

Connected to 1.5 V voltage regulator in Fusion device internally.

0 – Voltage regulator disables

1 – Voltage regulator enables

Note:

*Signals are hardwired internally and do not exist in the macro core.

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