AFS090 datasheet(44/334 Pages) MICROSEMI

44 / 334 page

Device Architecture

2- 28

R e visio n 2

CCC Physical Implementation

The CCC circuit is composed of the following (Figure 2-23):

•

PLL core

•

3 phase selectors

•

6 programmable delays and 1 fixed delay

•

5 programmable frequency dividers that provide frequency multiplication/division (not shown in

Figure 2-23 because they are automatically configured based on the user's required frequencies)

•

1 dynamic shift register that provides CCC dynamic reconfiguration capability (not shown)

CCC Programming

The CCC block is fully configurable. It is configured via static flash configuration bits in the array, set by

the user in the programming bitstream, or configured through an asynchronous dedicated shift register,

dynamically accessible from inside the Fusion device. The dedicated shift register permits changes of

parameters such as PLL divide ratios and delays during device operation. This latter mode allows the

user to dynamically reconfigure the PLL without the need for core programming. The register file is

accessed through a simple serial interface.

Note:

Clock divider and multiplier blocks are not shown in this figure or in SmartGen. They are

automatically configured based on the user's required frequencies.

Figure 2-23 • PLL Block

PLL Core

Phase

Select

Phase

Select

Phase

Select

GLA

CLKA

GLB

GLC

Fixed Delay

Programmable

Delay Type 1

Programmable

Delay Type 2

Programmable

Delay Type 2

Programmable

Delay Type 1

Programmable

Delay Type 2

Programmable

Delay Type 1

Four-Phase Output

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