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HD64F2149YV Folha de dados(PDF) 1017 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 1017 Page - Renesas Technology Corp

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Appendix B Internal I/O Registers
Rev. 3.00 Jan 18, 2006 page 989 of 1044
REJ09B0280-0300
SEDGR—Edge Sense Register
H'FFFF
Timer Connection
Bit
Initial value
Read/Write
7
VEDG
0
R/(W)
6
HEDG
0
R/(W)
5
CEDG
0
R/(W)
4
HFEDG
0
R/(W)
3
VFEDG
0
R/(W)
0
IVI
—*2
R
2
PREQF
0
R/(W)
1
IHI
—*2
R
*1
*1
*1
*1
*1
*1
IVI signal level
0
The IVI signal is low
1
The IVI signal is high
Notes: 1.
2.
IHI signal level
0
The IHI signal is low
1
The IHI signal is high
Pre-equalization flag
0
[Clearing condition]
When 0 is written in PREQF after
reading PREQF = 1
1
[Setting condition]
When an IHI signal 2fH modification
condition is detected
VFBACKI edge
0
[Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
1
[Setting condition]
When a rising edge is detected on the VFBACKI pin
HFBACKI edge
0
[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
1
[Setting condition]
When a rising edge is detected on the HFBACKI pin
CSYNCI edge
0
[Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
1
[Setting condition]
When a rising edge is detected on the CSYNCI pin
HSYNCI edge
0
[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
1
[Setting condition]
When a rising edge is detected on the HSYNCI pin
VSYNCI edge
0
[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
1
[Setting condition]
When a rising edge is detected on the VSYNCI pin
Only 0 can be written, to clear the flags.
The initial value is undefined since it depends on the pin states.



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