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HD64F2149YV Folha de dados(PDF) 974 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 974 Page - Renesas Technology Corp |
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974 / 1075 page ![]() Appendix B Internal I/O Registers Rev. 3.00 Jan 18, 2006 page 946 of 1044 REJ09B0280-0300 TCR—Timer Control Register H'FF96 FRT 7 IEDGA 0 R/W 6 IEDGB 0 R/W 5 IEDGC 0 R/W 4 IEDGD 0 R/W 3 BUFEA 0 R/W 0 CKS0 0 R/W 2 BUFEB 0 R/W 1 CKS1 0 R/W Bit Initial value Read/Write Input edge select A 0 Capture on the falling edge of FTIA Capture on the rising edge of FTIA 1 Input edge select B 0 Capture on the falling edge of FTIB Capture on the rising edge of FTIB 1 Input edge select C 0 Capture on the falling edge of FTIC Capture on the rising edge of FTIC 1 Input edge select D 0 Capture on the falling edge of FTID Capture on the rising edge of FTID 1 Buffer enable A 0 ICRC is not used as a buffer register for input capture A ICRC is used as a buffer register for input capture A 1 Buffer enable B 0 ICRD is not used as a buffer register for input capture B 1 Clock select 0 φ/2 internal clock source 0 1 φ/8 internal clock source φ/32 internal clock source External clock source (rising edge) 0 1 1 ICRD is used as a buffer register for input capture B |
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