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HD64F2149YV Folha de dados(PDF) 824 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 824 Page - Renesas Technology Corp |
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824 / 1075 page ![]() Section 25 Electrical Characteristics Rev. 3.00 Jan 18, 2006 page 796 of 1044 REJ09B0280-0300 Table 25.8 Timing of On-Chip Supporting Modules (2) Condition: V CC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, T a = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Test Conditions CS/HA0 setup time t HAR 10 — ns Figure 25.25 XBS read cycle CS/HA0 hold time t HRA 10 — ns IOR pulse width t HRPW 220 — ns HDB delay time t HRD — 200 ns HDB hold time t HRF 040 ns HIRQ delay time t HIRQ — 200 ns CS/HA0 setup time t HAW 10 — ns XBS write cycle CS/HA0 hold time t HWA 10 — ns IOW pulse width t HWPW 100 — ns HDB setup time Fast A20 gate not used t HDW 50 — ns Fast A20 gate used 85 — ns HDB hold time t HWD 25 — ns GA20 delay time t HGA — 180 ns |
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