HD64F2149YV datasheet(795/1075 Pages) RENESAS

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Section 24 Power-Down State

Rev. 3.00 Jan 18, 2006 page 767 of 1044

REJ09B0280-0300

24.9

Subsleep Mode

24.9.1

Subsleep Mode

If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0,

the LSON bit in LPWRCR is set to 1, and the PSS bit in TCSR (WDT1) is set to 1, the CPU

makes a transition to subsleep mode.

In this mode, the CPU and all on-chip supporting modules except TMR0, TMR1, WDT0, and

WDT1 stop. As long as the prescribed voltage is supplied, the contents of some of the CPU’s

internal registers and on-chip RAM are retained, and I/O ports retain their states prior to the

transition.

24.9.2

Clearing Subsleep Mode

Subsleep mode is cleared by an interrupt (on-chip supporting module interrupt, NMI pin, or pin

IRQ0 to IRQ7), or by means of the RES pin or STBY pin.

Clearing with an Interrupt: When an interrupt request signal is input, subsleep mode is cleared

and interrupt exception handling is started. Subsleep mode cannot be cleared with an IRQ0 to

IRQ7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting

module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable

Clearing with the

RES

RES Pin: See “Clearing with the RES Pin” in section 24.6.2, Clearing

Software Standby Mode.

Clearing with the

STBY

STBY Pin: When the STBY pin is driven low, a transition is made to hardware

standby mode

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