HD64F2149YV datasheet(789/1075 Pages) RENESAS

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Section 24 Power-Down State

Rev. 3.00 Jan 18, 2006 page 761 of 1044

REJ09B0280-0300

24.6

Software Standby Mode

24.6.1

Software Standby Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, the LSON bit in

LPWRCR is cleared to 0, and the PSS bit in TCSR (WDT1) is cleared to 0, software standby

mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.

However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip

supporting modules other than the SCI, PWM, and PWMX, and of the I/O ports, are retained.

In this mode the oscillator stops, and therefore power dissipation is significantly reduced.

24.6.2

Clearing Software Standby Mode

Software standby mode is cleared by an external interrupt (NMI pin, or pin

IRQ0 to IRQ2, IRQ6,

IRQ7), or by means of the RES pin or STBY pin.

Clearing with an Interrupt: When an NMI, IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt request

signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in

SYSCR, stable clocks are supplied to the entire chip, software standby mode is cleared, and

interrupt exception handling is started.

Software standby mode cannot be cleared with an IRQ0 to IRQ2, IRQ6, or IRQ7 interrupt if the

corresponding enable bit has been cleared to 0 or has been masked by the CPU.

Clearing with the

RES

RES Pin: When the RES pin is driven low, clock oscillation is started. At the

same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the

RES pin

must be held low until clock oscillation stabilizes. When the

RES pin goes high, the CPU begins

reset exception handling.

Clearing with the

STBY

STBY Pin: When the STBY pin is driven low, a transition is made to hardware

standby mode.

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