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HD64F2149YV Folha de dados(PDF) 773 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 773 Page - Renesas Technology Corp |
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773 / 1075 page ![]() Section 23 Clock Pulse Generator Rev. 3.00 Jan 18, 2006 page 745 of 1044 REJ09B0280-0300 WDT1, and I/O ports, operate on φ SUB clock. In addition, the count clock and sampling clock are derived by frequency division from φ SUB. Note: See figure 23.1. 23.10 X1 and X2 Pins Leave the X1 and X2 pins open, as shown in figure 23.9. X1 X2 Open Open Figure 23.9 X1 and X2 Pins |
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