HD64F2149YV datasheet(772/1075 Pages) RENESAS

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Section 23 Clock Pulse Generator

Rev. 3.00 Jan 18, 2006 page 744 of 1044

REJ09B0280-0300

tEXCLH

tEXCLL

tEXCLr

tEXCLf

VCC × 0.5

EXCL

Figure 23.8 Subclock Input Timing

When Subclock is not Needed: Do not enable subclock input when the subclock is not needed.

Note on Subclock Usage:

In transiting to power-down mode, if at least two cycles of the

32-kHz clock are not input after the 32-kHz clock input is enabled (EXCLE = 1) until the

SLEEP instruction is executed (power-down mode transition), the subclock input circuit is

not initialized and an error may occur in the microcomputer.

Before power-down mode is entered with using the subclock, at least two cycle of the 32-kHz

clock should be input after the 32-kHz clock input is enabled (EXCLE = 1).

As described in the hardware manual (clock pulse generator/subclock input circuit), when the

subclock is not used, the subclock input should not be enabled (EXCLE = 0).

23.8

Subclock Waveform Shaping Circuit

To eliminate noise in the subclock input from the EXCL pin, this circuit samples the clock using a

clock obtained by dividing the

φ clock. The sampling frequency is set with the NESEL bit in

LPWRCR. For details, see section 24.2.2, Low-Power Control Register (LPWRCR). The clock is

not sampled in subactive mode, subsleep mode, or watch mode.

23.9

Clock Selection Circuit

This circuit selects the system clock used in the MCU.

The clock signal generated in the EXTAL/XTAL oscillator is selected as a system clock, when the

MCU is returned from high-speed mode, medium-speed mode, sleep mode, reset state, standby

mode.

In sub-active mode, sub-sleep mode and watch mode, the sub-clock signal input from or EXCL

pin is selected as a sytem clock. In these modes, modules, such as CPU, TMR0, TMR1, WDT0,

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