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HD64F2149YV Folha de dados(PDF) 770 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 770 Page - Renesas Technology Corp |
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770 / 1075 page ![]() Section 23 Clock Pulse Generator Rev. 3.00 Jan 18, 2006 page 742 of 1044 REJ09B0280-0300 Table 23.5 External Clock Output Settling Delay Time Conditions: V CC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0 V Item Symbol Min Max Unit Notes External clock output settling delay time t DEXT* 500 — µs Figure 23.7 Note: * t DEXT includes RES pulse width (tRESW). tDEXT* RES (internal or external) EXTAL STBY VCC 2.7V VIH φ Note: * tDEXT includes RES pulse width (tRESW). Figure 23.7 External Clock Output Settling Delay Timing |
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