HD64F2149YV datasheet(746/1075 Pages) RENESAS

746 / 1075 page

Section 22 ROM

Rev. 3.00 Jan 18, 2006 page 718 of 1044

REJ09B0280-0300

• When a SLEEP instruction (including software standby, sleep, subactive, subsleep and watch

mode) is executed during programming/erasing

• When the bus is released during programming/erasing

Error protection is released only by a reset and in hardware standby mode.

Figure 22.14 shows the flash memory state transition diagram.

RD VF PR ER FLER = 0

Error

occurrence*1

RES = 0 or STBY = 0

RES = 0 or

STBY = 0

RD VF PR ER FLER = 0

Normal operation mode

Program mode

Erase mode

Reset or hardware standby

(hardware protection)

RD VF*4

PR ER FLER = 1

RD VF PR ER FLER = 1

Error protection mode

Error protection

mode (software standby,

sleep, subsleep, and watch )

Software standby,

sleep, subsleep, and

watch mode

FLMCR1, FLMCR2 (except

FLER bit), EBR1, EBR2

initialization state*3

FLMCR1,

FLMCR2,

EBR1, EBR2

initialization

state

Software standby,

sleep, subsleep, and

watch mode release

RD: Memory read possible

VF: Verify-read possible

PR: Programming possible

ER: Erasing possible

RD: Memory read not possible

VF: Verify-read not possible

PR: Programming not possible

ER: Erasing not possible

Legend:

RES = 0 or

STBY = 0

Error occurrence*2

Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is

executed for a transition to subactive mode

2. When an error occurs due to a SLEEP instruction (except subactive mode)

3. Except sleep mode

VF in subactive mode

Figure 22.14 Flash Memory State Transitions

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