HD64F2149YV datasheet(729/1075 Pages) RENESAS

729 / 1075 page

Section 22 ROM

Rev. 3.00 Jan 18, 2006 page 701 of 1044

REJ09B0280-0300

22.5.3

Erase Block Registers 1 and 2 (EBR1, EBR2)

Bit

543210

EBR1

——

——————

Initial value

000000

Read/Write

—*

Bit

543210

EBR2

EB7

EB6

EB5

EB4

EB3

EB2

EB1

EB0

Initial value

000000

Read/Write

R/W*

R/W

Notes: 1. In normal mode, these bits cannot be modified and are always read as 0.

2. This bit must not be set to 1.

EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 7 to 0

in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized to H'00 by a reset, in

hardware standby mode, software standby mode, subactive mode, subsleep mode, and watch

mode, and when the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the corresponding

block can be erased. Other blocks are erase-protected. Set only one bit in EBR2 (more than one bit

cannot be set). When on-chip flash memory is disabled, a read will return H'00, and writes are

invalid.

The flash memory block configuration is shown in table 22.6.

Table 22.6

Flash Memory Erase Blocks

Block (Size)

Address

EB0 (1 kbyte)

H'(00)0000 to H'(00)03FF

EB1 (1 kbyte)

H'(00)0400 to H'(00)07FF

EB2 (1 kbyte)

H'(00)0800 to H'(00)0BFF

EB3 (1 kbytes)

H'(00)0C00 to H'(00)0FFF

EB4 (28 kbytes)

H'(00)1000 to H'(00)7FFF

EB5 (16 kbytes)

H'(00)8000 to H'(00)BFFF

EB6 (8 kbytes)

H'(00)C000 to H'(00)DFFF

EB7 (8 kbytes)

H'00E000 to H'00FFFF

HD64F2149YV Folha de dados(PDF) 729 Page - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 729 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL