HD64F2149YV datasheet(699/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 20 A/D Converter

Rev. 3.00 Jan 18, 2006 page 671 of 1044

REJ09B0280-0300

20.3

Interface to Bus Master

ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide.

Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is

accessed via a temporary register (TEMP).

A data read from ADDR is performed as follows. When the upper byte is read, the upper byte

value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the

lower byte is read, the TEMP contents are transferred to the CPU.

When reading ADDR, always read the upper byte before the lower byte. It is possible to read only

the upper byte, but if only the lower byte is read, incorrect data may be obtained.

Figure 20.2 shows the data flow for ADDR access.

Bus master

(H'AA)

ADDRnH

(H'AA)

ADDRnL

(H'40)

Lower byte read

ADDRnH

(H'AA)

ADDRnL

(H'40)

TEMP

(H'40)

TEMP

(H'40)

(n = A to D)

Module data bus

Bus interface

Upper byte read

Bus master

(H'40)

Bus interface

Figure 20.2 ADDR Access Operation (Reading H'AA40)

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