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HD64F2149YV Folha de dados(PDF) 696 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 696 Page - Renesas Technology Corp |
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696 / 1075 page ![]() Section 20 A/D Converter Rev. 3.00 Jan 18, 2006 page 668 of 1044 REJ09B0280-0300 20.2.3 A/D Control Register (ADCR) 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 — 1 — 4 — 1 — 3 — 1 — 0 — 1 — 2 — 1 — 1 — 1 — Bit Initial value Read/Write ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode. Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped. Bit 7 Bit 6 TRGS1 TRGS0 Description 0 0 Start of A/D conversion by external trigger is disabled (Initial value) 1 Start of A/D conversion by external trigger is disabled 1 0 Start of A/D conversion by external trigger (8-bit timer) is enabled 1 Start of A/D conversion by external trigger pin is enabled Bits 5 to 0—Reserved: Always be read as 1, and cannot be modified. |
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