HD64F2149YV datasheet(541/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

Scroll/Zoom	100%

Fabricante Electrônico	RENESAS [Renesas Technology Corp]

Página de início	http://www.renesas.com

Logo

541 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 513 of 1044

REJ09B0280-0300

Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop

conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit

start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.

This bit is always read as 1. If 1 is written, the data is not stored.

Bit 0

SCP

Description

Writing 0 issues a start or stop condition, in combination with the BBSY flag

Reading always returns a value of 1

(Initial value)

Writing is ignored

16.2.6

2C Bus Status Register (ICSR)

Bit

Initial value

Read/Write

Note: * Only 0 can be written, to clear the flags.

ESTP

R/(W)*

STOP

R/(W)*

IRTR

R/(W)*

AASX

R/(W)*

ACKB

R/W

AAS

R/(W)*

ADZ

R/(W)*

ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge

confirmation and control.

ICSR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been

detected during frame transfer in I

2C bus format slave mode.

HD64F2149YV Folha de dados(PDF) 541 Page - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 541 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL