HD64F2149YV datasheet(537/1075 Pages) RENESAS

537 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 509 of 1044

REJ09B0280-0300

Bit 4

TRS

Description

Receive mode

(Initial value)

[Clearing conditions]

1. When 0 is written by software (in cases other than setting condition 3)

2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3)

3. When bus arbitration is lost after transmission is started in I

2C bus format master

mode

4. When the SW bit in DDCSWR changes from 1 to 0

Transmit mode

[Setting conditions]

1. When 1 is written by software (in cases other than clearing conditions 3 and 4)

2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3

and 4)

3. When a 1 is received as the R/W bit of the first frame in I

2C bus format slave mode

Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the

acknowledge bit returned from the receiving device when using the I

2C bus format is to be ignored

and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,

performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received

acknowledge bit is not indicated by the ACKB bit, which is always 0.

In the H8S/2169 or H8S/2149, the DTC can be used to perform continuous transfer. The DTC is

activated when the IRTR interrupt flag is set to 1 (IRTR is one of two interrupt flags, the other

being IRIC). When the ACKE bit is 0, the TDRE, IRIC, and IRTR flags are set on completion of

data transmission, regardless of the value of the acknowledge bit. When the ACKE bit is 1, the

TDRE, IRIC, and IRTR flags are set on completion of data transmission when the acknowledge

bit is 0, and the IRIC flag alone is set on completion of data transmission when the acknowledge

bit is 1.

When the DTC is activated, the TDRE, IRIC, and IRTR flags are cleared to 0 after the specified

number of data transfers have been executed. Consequently, interrupts are not generated during

continuous data transfer, but if data transmission is completed with a 1 acknowledge bit when the

ACKE bit is set to 1, the DTC is not activated and an interrupt is generated, if enabled.

Depending on the receiving device, the acknowledge bit may be significant, in indicating

completion of processing of the received data, for instance, or may be fixed at 1 and have no

significance.

HD64F2149YV Folha de dados(PDF) 537 Page - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 537 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL