HD64F2149YV datasheet(535/1075 Pages) RENESAS

535 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 507 of 1044

REJ09B0280-0300

Bit 7—I

2C Bus Interface Enable (ICE): Selects whether or not the I2C bus interface is to be

used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer

operations are enabled. When ICE is cleared to 0, the I

2C bus interface module is disabled and the

internal state is cleared.

The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can

be accessed when ICE is 1.

Bit 7

ICE

Description

2C bus interface module disabled, with SCL and SDA signal pins

set to port function

(Initial value)

2C bus interface module internal state initialized

SAR and SARX can be accessed

2C bus interface module enabled for transfer operations (pins SCL and SCA are

driving the bus)

ICMR and ICDR can be accessed

Bit 6—I

2C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I2C

bus interface to the CPU.

Bit 6

IEIC

Description

Interrupts disabled

(Initial value)

Interrupts enabled

Bit 5—Master/Slave Select (MST)

Bit 4—Transmit/Receive Select (TRS)

MST selects whether the I

2C bus interface operates in master mode or slave mode.

TRS selects whether the I

2C bus interface operates in transmit mode or receive mode.

In master mode with the I

2C bus format, when arbitration is lost, MST and TRS are both reset by

hardware, causing a transition to slave receive mode. In slave receive mode with the addressing

format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to

the R/

W bit in the first frame after a start condition.

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