HD64F2149YV datasheet(531/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 503 of 1044

REJ09B0280-0300

Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to

SVAX0, differing from the addresses of other slave devices connected to the I

2C bus.

Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in

DDCSWR to select the communication format.

• I2C bus format: addressing format with acknowledge bit

• Synchronous serial format: non-addressing format without acknowledge bit, for master mode

only

• Formatless mode: non-addressing format with or without acknowledge bit, slave mode only,

start/stop conditions not detected

The FSX bit also specifies whether or not SARX slave address recognition is performed in slave

mode. For details, see the description of the FS bit in SAR.

16.2.4

2C Bus Mode Register (ICMR)

Bit

Initial value

Read/Write

MLS

R/W

WAIT

R/W

CKS2

R/W

CKS1

R/W

CKS0

R/W

BC0

R/W

BC2

R/W

BC1

R/W

ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred

first, performs master mode wait control, and selects the master mode transfer clock frequency and

the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and

read only when the ICE bit is set to 1 in ICCR.

ICMR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or

LSB-first.

If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and

receive data are stored differently. Transmit data should be written justified toward the MSB side

when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB

side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.

Do not set this bit to 1 when the I

2C bus format is used.

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