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HD64F2149YV Folha de dados(PDF) 424 Page - Renesas Technology Corp |
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HD64F2149YV Folha de dados(HTML) 424 Page - Renesas Technology Corp |
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424 / 1075 page ![]() Section 13 Timer Connection Rev. 3.00 Jan 18, 2006 page 396 of 1044 REJ09B0280-0300 Table 13.3 Examples of TCR Settings Bit(s) Abbreviation Contents Description 7 6 5 CMIEB CMIEA OVIE 0 0 0 Interrupts due to compare-match and overflow are disabled 4 and 3 CCLR1, CCLR0 11 TCNT is cleared by the rising edge of the external reset signal (IHI signal) 2 to 0 CKS2 to CKS0 001 Incremented on internal clock: φ Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings φφφφ:10 MHz H'07 0.8 µs H'0F 1.6 µs H'1F 3.2 µs H'3F 6.4 µs H'7F 12.8 µs IHI signal IHI signal is tested at compare-match Counter reset caused by IHI signal Counter clear caused by TCNT overflow At the 2nd compare-match, IHI signal is not tested PDC signal TCNT TCORB (threshold) Figure 13.2 Timing Chart for PWM Decoding |
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