HD64F2149YV datasheet(421/1075 Pages) RENESAS

421 / 1075 page

Section 13 Timer Connection

Rev. 3.00 Jan 18, 2006 page 393 of 1044

REJ09B0280-0300

Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin.

Bit 3

VFEDG

Description

[Clearing condition]

When 0 is written in VFEDG after reading VFEDG = 1

(Initial value)

[Setting condition]

When a rising edge is detected on the VFBACKI pin

Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH

modification condition. The generation of a falling/rising edge in the IHI signal during a mask

interval is expressed as the occurrence of a 2fH modification condition. For details, see section

13.3.4, IHI Signal 2fH Modification.

Bit 2

PREQF

Description

[Clearing condition]

When 0 is written in PREQF after reading PREQF = 1

(Initial value)

[Setting condition]

When an IHI signal 2fH modification condition is detected

Bit 1—IHI Signal Level (IHI): Indicates the current level of the IHI signal. Signal source and

phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to

determine whether the input signal is positive or negative, then maintain the IHI signal at positive

phase by modifying TCONRI.

Bit 1

IHI

Description

The IHI signal is low

The IHI signal is high

Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and

phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to

determine whether the input signal is positive or negative, then maintain the IVI signal at positive

phase by modifying TCONRI.

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