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HD64F2149YV Folha de dados(PDF) 405 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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HD64F2149YV Folha de dados(HTML) 405 Page - Renesas Technology Corp

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Section 12 8-Bit Timers
Rev. 3.00 Jan 18, 2006 page 377 of 1044
REJ09B0280-0300
12.6.3
Contention between TCOR Write and Compare-Match
During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match
occurs and the compare-match signal is disabled. Figure 12.15 shows this operation.
With TMRX, an ICR input capture contends with a compare-match in the same way as with a
write to TCORC. In this case, the input capture has priority and the compare-match signal is
inhibited.
φ
Address
TCOR address
Internal write signal
TCNT
TCOR
NM
T1
T2
TCOR write cycle by CPU
TCOR write data
NN + 1
Compare-match signal
Prohibited
Figure 12.15 Contention between TCOR Write and Compare-Match



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