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HD64F2149YV Folha de dados(PDF) 397 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
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HD64F2149YV Folha de dados(HTML) 397 Page - Renesas Technology Corp

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Section 12 8-Bit Timers
Rev. 3.00 Jan 18, 2006 page 369 of 1044
REJ09B0280-0300
12.3.3
TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.7 shows the timing of this operation.
φ
Clear signal
External reset
input pin
TCNT
N
H'00
N – 1
Figure 12.7 Timing of Clearing by External Reset Input
12.3.4
Timing of Overflow Flag (OVF) Setting
OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
12.8 shows the timing of this operation.
φ
OVF
Overflow signal
TCNT
H'FF
H'00
Figure 12.8 Timing of OVF Setting



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