M32CSLASH8B datasheet(260/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 243 of 385

Figure 17.30

End

i = 0 to 4

NOTE:

1. The external clock synchronization function is determined by the combination of the SCLKDIV bit in the UiSMR register

and the SU1HIM bit in the UiSMR2 register. Refer to the table "

Clock-Divided Synchronous Function Select" for

details.

UiMR register: bits SMD2 to SMD0 = 001b

CKDIR bit = 1

IOPOL bit = 0

UiSMR register: bits 6 to 0 = 0000000b

SCLKDIV bit

UiC0 register: bits CLK1 and CLK0 = 00b

CRD bit = 1

NCH bit

CKPOL bit = 0

UFORM bit = 0

UiC1 register: TE bit = 0

RE bit = 0

UiIRS bit

UiRRM bit = 0

UiLCH bit = 0

SCLKSTPB bit = 0

Pin setting in the Function Select Registers

Transmit/receive operation starts when a trigger is input to the

CTSi pin after writing data to the UiTB register.

Read the UiRB register when a receive operation is completed.

UiSMR3 register = 00h

UiSMR4 register = 00h

UiSMR2 register: bits 6 to 0 = 0000000b

SU1HIM bit

UiBRG register = 00h

Start

Transmit operation enabled

Receive operation enabled

UiC1 register: TE bit = 1

RE bit = 1

Transmit interrupt priority level select bits

Interrupt not requested

SiTIC register: bits ILVL2 to ILVL0

IR bit = 0

Receive interrupt priority level select bits

Interrupt not requested

SiRIC register: bits ILVL2 to ILVL0

IR bit = 0

Clock synchronous mode

Select external clock

CTS function disabled

Data output select bit

Transmit operation disabled

Receive operation disabled

UARTi transmit interrupt source select bit

Clock-divided synchronization stopped

Clock division synchronous bit(1)

External clock synchronous enable bit(1)

Interrupt enabled

I flag = 1

Interrupt disabled

I flag = 0

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