M32CSLASH8B datasheet(262/406 Pages) RENESAS

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M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 245 of 385

17.1.6

Special Mode 4 (SIM Mode)

In SIM mode, the MCU can communicate with SIM interface devices using UART mode. Both direct and

inverse formats are available. The TXDi pin (i = 0 to 4) outputs a low-level (“L”) signal when a parity error is

detected.

Table 17.18 lists specifications of SIM mode. Table 17.19 list pin settings. Figure 17.32 lists register settings.

Figure 17.33 shows an example of SIM interface operation. Figure 17.34 shows an example of SIM interface

connection.

Table 17.18

SIM Mode Specifications

NOTES:

1. Bits CNT3 to CNT0 in the TCSPR register select no division (n = 0) or divide-by-2n (n = 1 to 15).

2. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC

Item

Specification

Data format

• Data length 8-bit UART mode

• One stop bit

• Direct format:

Parity: even

Data logic: direct (not inverted)

Bit order: LSB first

• Inverse format:

Parity: odd

Data logic: inverse (inverted)

Bit order: MSB first

Baud rate

Set the CKDIR bit in the UiMR register is 0 (internal clock):

fj / (16 (m + 1))

fj = f1, f8, f2n(1) m: setting value of the UiBRG register (00h to FFh)

Transmit/receive control

CTS/RTS function disabled

Transmit start condition

To start transmit operation, all of the following must be met:

• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)

• The TI bit in the UiC1 register is 0 (data in the UiTB register)

Receive start condition

To start receive operation, all of the following must be met:

• Set the RE bit in the UiC1 register to 1 (receive operation enabled)

• The start bit is detected

Interrupt request generation

timing

Transmit interrupt:

• Set the UiIRS bit in the UiC1 register to 1 (transmit operation completed)

when the stop bit is output from the UARTi transmit shift register

Receive interrupt:

• when data is transferred from the UARTi receive shift register to the UiRB register

(receive operation completed)

Error detection

• Overrun error(2)

Overrun error occurs when the preceding bit of the stop bit of the next data is

received before reading the UiRB register

• Framing error

Framing error occurs when the number of the stop bits set using the STPS bit in the

UiMR register is not detected

• Parity error

Parity error occurs when parity is enabled and the received data does not have the

correct even or odd parity set with the PRY bit in the UiMR register.

• Error sum flag

Error sum flag becomes 1 when an overrun, framing, or parity error occurs

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