M32CSLASH8B datasheet(261/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 244 of 385

Set the SU1HIM bit in the UiSMR2 register (i = 0 to 4) and the SCLKDIV bit in the UiSMR register to values

shown in Table 17.17, and apply a trigger signal to the CTSi pin. Then, the SCLKSTPB bit becomes 1 and a

transmit and receive operation starts. Either the same clock cycle as the external clock or the external clock

cycle divided by two can be selected for the serial clock.

When the SCLKSTPB bit in the UiC1 register is set to 0, a transmission and reception in progress stops

immediately.

Figure 17.31 shows an example of the clock-divided synchronous function.

Table 17.17

Clock-Divided Synchronous Function Select

Figure 17.31

Clock-Divided Synchronous Function

SCLKDIV bit in the

UiSMR register

SU1HIM bit in the

UiSMR2 register

Clock-Divided Synchronous Function

Not synchronized

Same clock cycle as the external clock

0 or 1

External clock cycle divided by 2

External clock

from the CLKi pin

Serial clock

TXDi

Trigger signal input

to the CTSi pin

i = 0 to 4

A: When the SCLKDIV bit in the UiSMR register is set to 0, and the SU1HIM bit in the UiSMR2 register is set to 1

B: When the SCLKDIV bit is set to 1, and SU1HIM bit is set to either 0 or 1.

TXDi

The clock is stopped by the

SCLKSTPB bit in the UiC1 register

More than 1 clock

cycle is required

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