M32CSLASH8B datasheet(258/406 Pages) RENESAS

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M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 241 of 385

17.1.5

Special Mode 3 (GCI Mode)

Full-duplex clock synchronous serial communications are allowed in this mode. When a trigger is input to the

CTSi (i = 0 to 4) pin, the internal clock which is synchronized with the continuous external clock is generated,

and a transmit and receive operation is started.

Table 17.15 lists specifications of GCI mode. Table 17.16 lists pin settings. Figure 17.30 shows register settings.

Table 17.15

GCI Mode Specifications

NOTE:

1. If an overrun error occurs, a read from the UiRB register returns undefined values. The IR bit in the SiRIC

Item

Specification

Data format

Data length: 8 bits long

Serial clock

Select the external clock

Set the CKDIR bit in the UiMR register (i = 0 to 4) to 1 (external clock).

When a trigger is input, the external clock or the clock divided by 2 becomes the

serial clock.

Transmit and receive start

condition

A transmit and receive operation starts when a trigger is input to the CTSi pin after all

the following are met:

• Set the TE bit in the UiC1 register to 1 (transmit operation enabled)

• The TI bit in the UiC1 register is 1 (data in the UiTB register)

• Set the RE bit in the UiC1 register to 1 (receive operation enabled)

• Set the SCLKSTPB bit in the UiC1 register is set to 0 (clock-divided

synchronization stopped)

The SCLKSTPB bit becomes 1 (clock-divided synchronization started) when a

trigger is input to the CTSi pin

Transmit and receive stop

condition

The SCLKSTPB bit in the UiC1 register is set to 0

Interrupt request generation

timing

Transmit interrupt (The UiIRS bit in the UiC1 register selects one of the following):

• The UiIRS bit is set to 0 (no data in the UiTB register):

when data is transferred from the UiTB register to the UARTi transmit shift register

(transmit operation started)

• The UiIRS bit is set to 1 (transmit operation completed):

when data transmit operation from the UARTi transmit shift register is completed

Receive interrupt:

• When data is transferred from the UARTi receive shift register to the UiRB register

(receive operation completed)

Error detection

Overrun error(1)

Overrun error occurs when the 7th bit of the next data is received before reading the

UiRB register

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