M32CSLASH8B datasheet(256/406 Pages) RENESAS

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M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 239 of 385

17.1.4.1 Master Mode

Master mode is entered when the DINC bit in the UiSMR3 register (i = 0 to 4) is set to 1. The following pins are

used in master mode.

• TXDi: transmit data output

• RXDi: receive data input

• CLKi: serial clock output

To use the SS function, set the SSE bit in the UiSMR3 register to 1. A transmit and receive operation is

performed while an “H” is applied to the SSi pin. If an “L” is applied to the SSi pin, the ERR bit in the UiSMR3

UiIRS bit in the UiC1 register to 1 (Transmit completion as interrupt source) to verify whether a mode error has

occurred or not by checking the EER bit in the transmission complete interrupt routine. To resume serial

communication after a mode error occurs, set the ERR bit to 0 (no mode error) while an “H” signal is applied to

the SSi pin. Pins TXDi and CLKi become in output mode.

17.1.4.2 Slave Mode

Slave mode is entered when the DINC bit in the UiSMR3 register is set to 0. The following pins are used in

slave mode.

• STXDi: transmit data output

• SRXDi: receive data input

• CLKi: serial clock input

To use the SS function, set the SSE bit in the UiSMR3 register to 1. When an “L” signal is applied to the SSi

input pin, the serial clock input is enabled, and a transmit and receive operation becomes available. When an

“H” signal is applied to the SSi pin, the serial clock input to the CLKi pin is ignored and the STXDi pin is

placed in a high-impedance state.

Figure 17.28

Serial Bus Communication Control with SSi Pin

MCU

P1_3

P1_2

P9_3(SS3)

P9_0(CLK3)

P9_1(RXD3)

P9_2(TXD3)

MCU

(Slave)

(Master)

P9_3(SS3)

P9_0(CLK3)

P9_1(STXD3)

P9_2(SRXD3)

P9_3(SS3)

P9_0(CLK3)

P9_1(STXD3)

P9_2(SRXD3)

(Slave)

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