M32CSLASH8B datasheet(255/406 Pages) RENESAS

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Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 238 of 385

Figure 17.27

End

i = 0 to 4

NOTES:

1. Set to 0 in master mode, and set to 1 in slave mode.

2. The clock phase is determined by the combination of the CKPH and CKPOL bits in the UiSMR3 register.

3. Bits CNT3 to CNT0 select no division (n = 0) or divide-by-2n (n = 1 to 15).

UiMR register: bits SMD2 to SMD0 = 001b

CKDIR bit

IOPOL bit = 0

Clock synchronous mode

Clock select bit(1)

UiSMR register = 00h

UiSMR2 register = 00h

UiSMR4 register = 00h

UiC0 register: bits CLK1 to CLK0

CRD bit = 1

NCH bit

CKPOL bit

UFORM bit

UiBRG count source select bits

CTS function disabled

Data output select bit

CLK polarity select bit(2)

Bit order select bit

m = 00h to FFh

Baud rate =

UiC1 register: TE bit = 0

RE bit = 0

UiIRS bit

UiRRM bit = 0

UiLCH bit = 0

bit 7 = 0

Transmit operation disabled

Receive operation disabled

UARTi transmit interrupt souce select bit

Pin setting in the Function Select Registers

2(m + 1)

fj: f1, f8, f2n(3)

When an internal clock is used

Transmit/receive operation starts by writing data to UiTB register.

Read the UiRB register when the receive operation is completed.

UiSMR3 register: SSE bit = 1

CKPH bit

DINC bit

NODC bit = 0

bits DL2 to DL0 = 000b

SS function enabled

Clock phase set bit(2)

Serial I/O pin set bit(1)

Start

Transmit operation enabled

Receive operation enabled

UiC1 register: TE bit = 1

RE bit = 1

Transmit interrupt priority level select bit

Interrupt not requested

SiTIC register: bits ILVL2 to ILVL0

IR bit = 0

Receive interrupt priority level select bit

Interrupt not requested

SiRIC register: bits ILVL2 to ILVL0

IR bit = 0

Interrupt enabled

I flag = 1

Interrupt disabled

I flag = 0

UiBRG register = m

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