AS3953A-BDFM datasheet(16/71 Pages) AMSOSRAM

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[v1-05] 2019-Feb-15

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AS3953A − Detailed Description

ISO 14443A Framing Mode

When Framing mode is selected the PICC logic performs receive

and transmit framing according to the selected ISO 14443A bit

rate.

During reception it recognizes the SOF, EOF and data bits,

performs parity and CRC check, organizes the received data in

bytes and places them in the FIFO.

During transmit, it operates inversely, it takes bytes from FIFO,

generates parity and CRC bits, adds SOF and EOF and performs

data encoding.

Default bit rate in the Framing mode is fc/128 (~106 kbit/s).

Higher data rates may be configured by controller by writing

the Bit Rate Definition Register.

In order to respect the PCD-to-PICC frame delay according to

ISO14443-3 at data rate fc/128 bit the PICC logic synchronizes

the response to the beginning of the next response window,

but not earlier than window with n=9.

In this mode the EEPROM can be accessed via SPI when the RF

field is active.

ISO 14443A Level-4 Protocol Mode

When Level-4 Protocol mode is selected the PICC Logic

autonomously execute complete ISO 14443A Level-3

communication and certain commands of Level-4. This also

includes the anti-collision sequence during which the AS3953A

UID number is read by the PCD (7 bytes UID is supported), the

AS3953A is brought in the selected state (ISO14443-4) in which

data exchange between the AS3953A and the PCD can start. On

this level also a reading and writing of the AS3953A EEPROM is

possible.

In case the configuration bit irq_l4 is set an interrupt is

automatically sent to controller once the PICC Logic enters in

ACTIVE(*) state (after sending SAK on Cascade Level 2).

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