AS3953A-BDFM datasheet(56/71 Pages) AMSOSRAM

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ams Datasheet

Page 55

[v1-05] 2019-Feb-15

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AS3953A − Detailed Description

Figure 62:

Main Interrupt Register

Notes:

1. At power-up and after Set Default command, content of this register is set to ‘0’.

2. After Main Interrupt Register is read, with the exception of bit0, the register content is set to ‘0’. The bit0 is set to ‘0’ only after the

corresponding interrupt register is read.

Address# 0Ah: Main Interrupt

Type: R

Bit

Name

Function

Comments

7I_pu

Power-up IRQ

I_wu_l4

Wake-up IRQ at entry in ACTIVE(*) state

5I_wu

Wake-up IRQ triggered by sending

Wake-Up command

I_rxs

IRQ due to start of receive

Applicable when receive frame is

put in FIFO

I_rxe

IRQ due to end of receive

Applicable when receive frame is

put in FIFO

I_txe

IRQ due to end of transmission

Applicable when data from FIFO is

sent

I_wl

IRQ due to FIFO water level

During receive informing that

FIFO is almost full and has to be

read out.

During transmit informing that

FIFO is almost empty and that

additional data has to be send

0I_aux

IRQ due to event displayed in the

Auxiliary Interrupt Register

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