AS3953A-BDFM datasheet(37/71 Pages) AMSOSRAM

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[v1-05] 2019-Feb-15

AS3953A − Detailed Description

Reading of Data from Addressable Registers (Register

Read Mode)

After the SPI operation mode bits the address of register to be

read has to be provided from the MSB to the LSB. Then one or

more data bytes are transferred to MISO output, always from

the MSB to the LSB. As in case of the write mode also the read

mode supports auto-incrementing address.

MOSI is sampled at the falling edge of SCLK (like shown in the

following diagrams); data to be read from the AS3953A internal

sampled by the master at the falling edge of SCLK.

In case the register on defined address does not exist all ‘0’ data

is sent to MISO.

In the following figure example for reading of single byte is

given.

Figure 44:

Reading of a Single Register

SCLK rising

edge Data is

moved from

Address

<A4-A0>

/SS rising

edge signals

end of READ

Mode

Three leading

bits indicate

Mode

SCLK rising

edge Data is

transfered

from µC

SCLK falling

edge Data is

sampled

SCLK falling

edge Data is

transfered to

µC

/SS

SCLK

MOSI

MISO

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