AS3953A-BDFM datasheet(34/71 Pages) AMSOSRAM

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Page 33

[v1-05] 2019-Feb-15

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AS3953A − Detailed Description

SPI Interface

Communication between the AS3953A and controller is done

through a 4-wire Serial Peripheral Interface (SPI) and additional

interrupt signal. The AS3953A is an SPI slave device; it requests

controller attention by sending an interrupt (IRQ pin).

Figure 39:

SPI and Interrupt Signals

While signal /SS is high the SPI interface is in reset, while it is

low the SPI interface is enabled. It is recommended to keep

signal /SS high whenever the SPI interface is not in use. MOSI is

sampled at the falling edge of SCLK. All communication is done

in blocks of 8 bits (bytes). First three bits of first byte transmitted

after high to low transition of /SS define SPI operation mode.

MSB bit is always transmitted first (valid for address and data).

Read and Write modes support address auto incrementing,

which means that in case after the address and first data byte

some additional data bytes are sent (read), they are written to

(read from) addresses incremented by ‘1’.

SPI interface supports the following modes:

• Read and write of the SPI Interface internal registers

• Read and write of the EEPROM

• Read and write of the FIFO

• Sending direct commands

Please note that the only SPI operations, which are allowed

when logic and EEPROM are supplied from VP_SPI, are reading

and writing of EEPROM and registers (see also Power Manager).

Name

Signal

Signal Level

Description

/SS

Digital input with pull-up

CMOS

SPI enable (active low)

MOSI

Digital input

CMOS

Serial data input

MISO

Digital output with

tristate

CMOS

Serial data output

SCLK

Digital input

CMOS

Clock for serial communication

IRQ

Digital output

CMOS

Interrupt output pin

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