AS3418 datasheet(51/78 Pages) AMSOSRAM

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AS3418

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

│ 50

Addr: 0x01

SYSTEM_STATUS

Bit

Bit Name

Default

Access

Bit Description

works only if the I2C_MODE bit is set. In case

I2C_MODE is low, the register content is ignored.

0: Power up hold is cleared and chip powers down

1: Device remains powered on

Figure 69:

MODE_REG0 Register Description

Addr: 0x02

MODE_REG0

Bit

Bit Name

Default

Access

Bit Description

EN_ZERO_C

ROSS

R/W

This bit activates zero cross detection while switching

between music bypass switch and headphone

amplifier.

0: Zero cross detection is disabled.

1: Zero cross detection is enabled.

DELAY_HPH_

MUX

R/W

This register controls the startup delay setting before

the ANC_HPH_MUX setting is applied to the system.

This function can help to reduce pop noise during

startup of the device especially if there are

components with long charging times involved. This

bit is only valid during initial startup.

0: Headphone MUX delay disabled

1: Headphone MUX delay enabled

4:3

UI_MODE

R/W

This register defines the user interface operation

mode of AS3418. For a detailed description of the

different user interface modes please refer to chapter

Operation Modes.

00: Push Button Operation Mode

01: Slider Operation Mode

10: Full Slider Operation

11: Do not use

MICS_DC_EN

R/W

This bit enables the internal microphone supply

discharge function if the microphone supply is

switched off. The MICS_LDO pin is discharged within

~10ms.

0: MICS_LDO discharge disabled

1: MICS_LDO discharge enabled

HPH_MODE

R/W

This register controls the operation mode of the

headphone amplifier. The headphone amplifier

supports single ended mode and differential mode. In

differential output mode the right audio signal path is

the active input signal for the headphone amplifier.

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