AS3418 datasheet(50/78 Pages) AMSOSRAM

50 / 78 page

Document Feedback

AS3418

Datasheet

• PUBLIC

DS000507

• v4-00 • 2020-Jan-23

│ 49

7.2

Detailed Register Description

7.2.1

System Registers

Figure 67:

ID Register Description

Addr: 0x00

Bit

Bit Name

Default

Access

Bit Description

7:4

DESIGN_VER

SION

0110

Design version number to identify the design version

of the AS3418.

0110: Chip Version 3.0

3:0

CHIP_ID

0001

This register represents the chip ID number of

AS3418.

0001: AS3418

Figure 68:

SYSTEM_STATUS Register Description

Addr: 0x01

SYSTEM_STATUS

Bit

Bit Name

Default

Access

Bit Description

EE_WR_TEST

_OK

This register reports if an EEPROM upload test was

successfully finished. This bit is also used for the

EEPROM-Program-Test (together with

EEPROM_UPLOAD_TEST

), where a “dummy-write”

can be initialized to check the power-supply

0: EEPROM upload TEST failed

1: EEPROM upload TEST successful

EE_READY

This registers indicates the status after a read/write

command of the EEPROM.

0: EEPROM busy

1: EEPROM ready

PWRUP_COM

PLETE

This bit indicates the Power-Up sequencer status of

AS3418. The signal goes high after all amplifiers are

enabled but before the microphone signal is faded in.

0: Power-up sequence incomplete

1: Power-up sequence completed

PWR_HOLD

R/W

This bit allows an MCU, using the I2C interface, to

power down the AS3418. A start condition on the I2C

interface will wake up the device again. This function

AS3418 Folha de dados(PDF) 50 Page - ams-OSRAM AG

AS3418 Folha de dados(HTML) 50 Page - ams-OSRAM AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

Folha de dados Download

Ligação URL