CC1010-RTY1 datasheet(102/150 Pages) TI2

102 / 150 page

CC1010

SWRS047A

Page 102 of 146

17.10 Synchronization and preamble detection

Most RF communication protocols will

have a preamble designated to let the

receiver synchronise reception on a bit

and byte level.

CC1010 contains hardware

that will perform these tasks easily in

synchronous

NRZ

and

Manchester

encoded modes.

The

byte

synchronization

mechanism

ensures that the framing of bytes in the

received data bit stream is correct, thus

freeing the software from needing to

perform shifting and recombination of data

bytes. In addition, the synchronization byte

functions as a start of frame delimiter. The

preamble detection mechanism reduces

the workload for the processor when the

exact time of the start of a transmission is

uncertain. Both mechanisms are active

when

PDET.PEN

set.

(See

PDET

examples are shown in Figure 29. Note

that the Manchester baud rate is twice the

NRZ baud rate in the figure.

The

preamble

must

consist

alternating

0-1-pattern

followed

synchronization byte of eight bits. Unless

the average filter is already locked at the

arrival of the synchronization byte in NRZ

mode, it is vital that the synchronization

byte is DC-balanced (equal number of

zeros and ones) and contains no more

than two consecutive ones or zeros. It is

also required that the synchronization byte

contains two consecutive ones or zeros.

This means that e.g. 0xCC is not a legal

synchronization byte, but 0xCA is.

NRZ

Byte sync

Data

Preamble

Bit value

Manchester

Bit value

Figure 29. Preamble detection examples

PDET (0xD3) - Preamble Detection Control Register

Bit

Name

R/W

Reset value

Description

PEN

R/W

Preamble and byte synchronisation enable.

0 : Receiver mode is defined by RFCON.BYTEMODE.

1 : Preamble and byte synchronisation is enabled.

RFCON.BYTEMODE

is don't care.

6:0

PLEN

R/W

0x00

Preamble length.

Define the number of alternating bits required before byte

synchronisation. PLEN must be greater than zero.

BSYNC (0xD4) - Byte Synchronisation Register

Bit

Name

R/W

Reset value

Description

7:0

BSYNC(7:0)

R/W

0x00

BSYNC

defines the byte that triggers byte

synchronisation during RF preamble detection.

The

hardware

support

for

preamble

detection consists of a seven-bit counter,

which keeps track of the number of

successive alternating bits. It is reset

CC1010-RTY1 Folha de dados(PDF) 102 Page - Texas Instruments

CC1010-RTY1 Folha de dados(HTML) 102 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL