CC1010-RTY1 datasheet(59/150 Pages) TI2

59 / 150 page

CC1010

SWRS047A

Page 59 of 146

16.3 Timer 2 / 3 with PWM

CC1010 also features two timers with pulse

width modulation (PWM) outputs. Each

timer

can

generate

interrupts,

described in the Interrupts section on page

28. The timers are individually set in one

of two modes, timer mode or PWM mode.

This is controlled through the bits M2 and

in the TCON2 control register shown

below.

Timer

and

Timer

are

enabled

individually through the bits TCON2.TR2

and TCON2.TR3.

TCON2 (0xA9) - Timer Control register 2

Bit

Name

R/W

Reset value

Description

Reserved, read as 0

TR3

R/W

Timer 3 run control

0 : Timer 3 is disabled. The Timer 3 counter is cleared.

1 : Timer 3 is enabled.

R/W

Timer 3 mode control.

0 : Timer 3 is in timer mode.

1 : Timer 3 is in PWM mode. P3.5 is set to be an output,

overriding P3DIR(5)

TR2

R/W

Timer 2 run control

0 : Timer 2 is disabled. The Timer 2 counter is cleared.

1 : Timer 2 is enabled.

R/W

Timer 2 mode control.

0 : Timer 2 is in timer mode.

1 : Timer 2 is in PWM mode. P3.4 is set to be an output,

overriding P3DIR(4)

16.3.1

Timer Mode

Timer 2 / Timer 3 can be set in Timer

Mode by clearing the bit TCON2.M2 /

TCON2.M3

Timer

Mode

operation

illustrated in Figure 11. The 16 bit counter

is preloaded with T2 and T2PRE (or T3

and T3PRE) as shown. When disabling the

timer through clearing TCON2.TR2 (or

TCON2.TR3

)

the

counter

also

preloaded. The counter value cannot be

read by software.

When the counter underflows (decrements

from a zero value), it is loaded with the

contents of T2 / T3 and T2PRE / T3PRE,

and the interrupt request bit EXIF.TF2 /

EXIF.TF3

set

hardware.

The

interrupt request must be cleared by

software.

In Timer mode, interrupts are generated

with an interval as given by TnINT , where

⊆{2,3} :

(

)

system

nInt

256

255

⋅

TnPRE

As long as TnPRE and Tn are set before

TCON.TRn

, the first interrupt is generated

TnINT after enabling the timer and then with

TnINT intervals.

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