HCS08 datasheet(148/198 Pages) NXP

148 / 198 page

Timer/Pulse-Width Modulator (S08TPMV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

148

Freescale Semiconductor

Freescale-provided equate or header file is used to translate these names into the appropriate absolute

addresses.

11.3.1

Timer Status and Control Register (TPMxSC)

TPMxSC contains the overflow status flag and control bits that are used to configure the interrupt enable,

TPM configuration, clock source, and prescale divisor. These controls relate to all channels within this

timer module.

321

RTOF

TOIE

CPWMS

CLKSB

CLKSA

PS2

PS1

PS0

Reset

000

= Unimplemented or Reserved

Figure 11-3. Timer Status and Control Register (TPMxSC)

Table 11-1. TPMxSC Register Field Descriptions

Field

Description

TOF

Timer Overflow Flag — This flag is set when the TPM counter changes to 0x0000 after reaching the modulo

value programmed in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after

the counter has reached the value in the modulo register, at the transition to the next lower count value. Clear

TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF. If another TPM

overflow occurs before the clearing sequence is complete, the sequence is reset so TOF would remain set after

the clear sequence was completed for the earlier TOF. Reset clears TOF. Writing a 1 to TOF has no effect.

0 TPM counter has not reached modulo value or overflow

1 TPM counter has overflowed

TOIE

Timer Overflow Interrupt Enable — This read/write bit enables TPM overflow interrupts. If TOIE is set, an

interrupt is generated when TOF equals 1. Reset clears TOIE.

0 TOF interrupts inhibited (use software polling)

1 TOF interrupts enabled

CPWMS

Center-Aligned PWM Select — This read/write bit selects CPWM operating mode. Reset clears this bit so the

TPM operates in up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting

CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset clears

CPWMS.

0 All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as selected by the

MSnB:MSnA control bits in each channel’s status and control register

1 All TPMx channels operate in center-aligned PWM mode

4:3

CLKS[B:A]

Clock Source Select — As shown in Table 11-2, this 2-bit field is used to disable the TPM system or select one

of three clock sources to drive the counter prescaler. The external source and the XCLK are synchronized to the

bus clock by an on-chip synchronization circuit.

2:0

PS[2:0]

Prescale Divisor Select — This 3-bit field selects one of eight divisors for the TPM clock input as shown in

Table 11-3. This prescaler is located after any clock source synchronization or clock source selection, so it affects

whatever clock source is selected to drive the TPM system.

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