HCS08 datasheet(45/198 Pages) NXP

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Chapter 4 Memory Map and Register Definition

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

if PRDIV8 = 0 – fFCLK = fBus ÷ (DIV + 1)

Eqn. 4-1

if PRDIV8 = 1 – fFCLK = fBus ÷ (8 × (DIV + 1))

Eqn. 4-2

Table 4-7 shows the appropriate values for PRDIV8 and DIV for selected bus frequencies.

321

RDIVLD

PRDIV8

DIV

Reset

000

= Unimplemented or Reserved

Figure 4-5. Flash Clock Divider Register (FCDIV)

Table 4-6. FCDIV Register Field Descriptions

Field

Description

DIVLD

Divisor Loaded Status Flag — When set, this read-only status flag indicates that the FCDIV register has been

written since reset. Reset clears this bit and the first write to this register causes this bit to become set regardless

of the data written.

0 FCDIV has not been written since reset; erase and program operations disabled for flash.

1 FCDIV has been written since reset; erase and program operations enabled for flash.

PRDIV8

Prescale (Divide) Flash Clock by 8

0 Clock input to the flash clock divider is the bus rate clock.

1 Clock input to the flash clock divider is the bus rate clock divided by 8.

5:0

DIV

Divisor for Flash Clock Divider — The flash clock divider divides the bus rate clock (or the bus rate clock

divided by 8 if PRDIV8 = 1) by the value in the 6-bit DIV field plus one. The resulting frequency of the internal

flash clock must fall within the range of 200 kHz to 150 kHz for proper flash operations. Program/Erase timing

pulses are one cycle of this internal flash clock which corresponds to a range of 5

μs to 6.7 μs. The automated

programming logic uses an integer number of these pulses to complete an erase or program operation. See

Equation 4-1 and Equation 4-2.

Table 4-7. Flash Clock Divider Settings

fBus

PRDIV8

(Binary)

DIV

(Decimal)

fFCLK

Program/Erase Timing Pulse

μs Min, 6.7 μs Max)

8 MHz

200 kHz

μs

4 MHz

200 kHz

μs

2 MHz

200 kHz

μs

1 MHz

200 kHz

μs

200 kHz

μs

150 kHz

6.7

μs

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