HCS08 datasheet(59/198 Pages) NXP

59 / 198 page

Chapter 5 Resets, Interrupts, and General System Control

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

5.8.2

System Reset Status Register (SRS)

This high-page register includes read-only status flags to indicate the source of the most recent reset. When

a debug host forces reset by writing 1 to BDFR in the SBDFR register, all of the status bits in SRS will be

cleared. Writing any value to this register address clears the COP watchdog timer without affecting the

contents of this register. The reset state of these bits depends on what caused the MCU to reset.

IRQACK

IRQ Acknowledge — This write-only bit is used to acknowledge interrupt request events (write 1 to clear IRQF).

Writing 0 has no meaning or effect. Reads always return 0. If edge-and-level detection is selected (IRQMOD = 1),

IRQF cannot be cleared while the IRQ pin remains at its asserted level.

IRQIE

IRQ Interrupt Enable — This read/write control bit determines whether IRQ events generate an interrupt

request.

0 Interrupt request when IRQF set is disabled (use polling).

1 Interrupt requested whenever IRQF = 1.

IRQMOD

IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level

detection. The IRQEDG control bit determines the polarity of edges and levels that are detected as interrupt

request events. See Section 5.5.2.2, “Edge and Level Sensitivity,” for more details.

0 IRQ event on falling edges or rising edges only.

1 IRQ event on falling edges and low levels or on rising edges and high levels.

321

POR

COP

ILOP

ILAD

LVD

Writing any value to SRS address clears COP watchdog timer.

POR:

100

010

LVR:

000

010

Any

other

reset:

(1)(1)(1)(1)

000

1 Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits

corresponding to sources that are not active at the time of reset entry will be cleared.

Figure 5-3. System Reset Status (SRS)

Table 5-4. SRS Register Field Descriptions

Field

Description

POR

Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was

ramping up at the time, the low-voltage reset (LVR) status bit is also set to indicate that the reset occurred while

the internal supply was below the LVR threshold.

0 Reset not caused by POR.

1 POR caused reset.

External Reset Pin — Reset was caused by an active-low level on the external reset pin.

0 Reset not caused by external reset pin.

1 Reset came from external reset pin.

Table 5-3. IRQSC Register Field Descriptions (continued)

Field

Description

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