HCS08 datasheet(108/198 Pages) NXP

108 / 198 page

Analog-to-Digital Converter (S08ADC10V1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

108

Freescale Semiconductor

8.4

Functional Description

The ADC module is disabled during reset or when the ADCH bits are all high. The module is idle when a

conversion has completed and another conversion has not been initiated. When idle, the module is in its

lowest power state.

The ADC can perform an analog-to-digital conversion on any of the software selectable channels. The

selected channel voltage is converted by a successive approximation algorithm into an 11-bit digital result.

In 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a

9-bit digital result.

When the conversion is completed, the result is placed in the data registers (ADCRH and ADCRL).In

10-bit mode, the result is rounded to 10 bits and placed in ADCRH and ADCRL. In 8-bit mode, the result

is rounded to 8 bits and placed in ADCRL. The conversion complete flag (COCO) is then set and an

interrupt is generated if the conversion complete interrupt has been enabled (AIEN = 1).

The ADC module has the capability of automatically comparing the result of a conversion with the

contents of its compare registers. The compare function is enabled by setting the ACFE bit and operates

in conjunction with any of the conversion modes and configurations.

8.4.1

Clock Select and Divide Control

One of four clock sources can be selected as the clock source for the ADC module. This clock source is

then divided by a configurable value to generate the input clock to the converter (ADCK). The clock is

selected from one of the following sources by means of the ADICLK bits.

•

The bus clock, which is equal to the frequency at which software is executed. This is the default

selection following reset.

•

The bus clock divided by 2. For higher bus clock rates, this allows a maximum divide by 16 of the

bus clock.

•

ALTCLK, as defined for this MCU (See module section introduction).

•

The asynchronous clock (ADACK) – This clock is generated from a clock source within the ADC

module. When selected as the clock source this clock remains active while the MCU is in wait or

stop3 mode and allows conversions in these modes for lower noise operation.

Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the

available clocks are too slow, the ADC will not perform according to specifications. If the available clocks

ADPC17

ADC Pin Control 17 — ADPC17 is used to control the pin associated with channel AD17.

0 AD17 pin I/O control enabled

1 AD17 pin I/O control disabled

ADPC16

ADC Pin Control 16 — ADPC16 is used to control the pin associated with channel AD16.

0 AD16 pin I/O control enabled

1 AD16 pin I/O control disabled

Table 8-11. APCTL3 Register Field Descriptions (continued)

Field

Description

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