HCS08 datasheet(162/198 Pages) NXP

162 / 198 page

Development Support

MC9S08QD4 Series MCU Data Sheet, Rev. 6

162

Freescale Semiconductor

when this timeout occurs is aborted without affecting the memory or operating mode of the target MCU

system.

The custom serial protocol requires the debug pod to know the target BDC communication clock speed.

The clock switch (CLKSW) control bit in the BDC status and control register allows the user to select the

BDC clock source. The BDC clock source can either be the bus or the alternate BDC clock source.

The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams

show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but

asynchronous to the external host. The internal BDC clock signal is shown for reference in counting

cycles.

Figure 12-2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU.

The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge

to where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target

senses the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin

during host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD

pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal

during this period.

Figure 12-2. BDC Host-to-Target Serial Bit Timing

Figure 12-3 shows the host receiving a logic 1 from the target HCS08 MCU. Because the host is

asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on

BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long

enough for the target to recognize it (at least two target BDC cycles). The host must release the low drive

before the target MCU drives a brief active-high speedup pulse seven cycles after the perceived start of the

bit time. The host must sample the bit level about 10 cycles after it started the bit time.

EARLIEST START

TARGET SENSES BIT LEVEL

10 CYCLES

SYNCHRONIZATION

UNCERTAINTY

BDC CLOCK

(TARGET MCU)

HOST

TRANSMIT 1

HOST

TRANSMIT 0

PERCEIVED START

OF BIT TIME

OF NEXT BIT

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