HCS08 datasheet(155/198 Pages) NXP

155 / 198 page

Timer/Pulse-Width Modulator (S08TPMV2)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

Freescale Semiconductor

155

11.4.2.2

Output Compare Mode

With the output compare function, the TPM can generate timed pulses with programmable position,

polarity, duration, and frequency. When the counter reaches the value in the channel value registers of an

output compare channel, the TPM can set, clear, or toggle the channel pin.

In output compare mode, values are transferred to the corresponding timer channel value registers only

after both 8-bit bytes of a 16-bit register have been written. This coherency sequence can be manually reset

by writing to the channel status/control register (TPMxCnSC).

An output compare event sets a flag bit (CHnF) that can optionally generate a CPU interrupt request.

11.4.2.3

Edge-Aligned PWM Mode

This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS = 0) and can

be used when other channels in the same TPM are configured for input capture or output compare

functions. The period of this PWM signal is determined by the setting in the modulus register

(TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value

ELSnA control bit. Duty cycle cases of 0 percent and 100 percent are possible.

As Figure 11-11 shows, the output compare value in the TPM channel registers determines the pulse width

(duty cycle) of the PWM signal. The time between the modulus overflow and the output compare is the

pulse width. If ELSnA = 0, the counter overflow forces the PWM signal high and the output compare

forces the PWM signal low. If ELSnA = 1, the counter overflow forces the PWM signal low and the output

compare forces the PWM signal high.

Figure 11-11. PWM Period and Pulse Width (ELSnA = 0)

When the channel value register is set to 0x0000, the duty cycle is 0 percent. By setting the timer channel

value register (TPMxCnVH:TPMxCnVL) to a value greater than the modulus setting, 100% duty cycle

can be achieved. This implies that the modulus setting must be less than 0xFFFF to get 100% duty cycle.

Because the HCS08 is a family of 8-bit MCUs, the settings in the timer channel registers are buffered to

ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to either register,

TPMxCnVH or TPMxCnVL, write to buffer registers. In edge-PWM mode, values are transferred to the

corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and

the value in the TPMxCNTH:TPMxCNTL counter is 0x0000. (The new duty cycle does not take effect

until the next full period.)

PERIOD

PULSE

WIDTH

OVERFLOW

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

TPMxC

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