ADIN1101BCPZ-R7 datasheet(19/79 Pages) AD

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Data Sheet

ADIN1101

THEORY OF OPERATION

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Rev. A | 19 of 79

Table 13. LED_0 Pin Configuration Summary (Continued)

Parameter

LED_0

Enable LED

LED0_EN bit (see the LED Control Register section)

LED Polarity

LED0_POLARITY bits (see the LED Polarity Register section)

LED Mode

LED0_MODE bit (see the LED Control Register section), default: LED Mode 1

LED Function1

LED0_FUNCTION bits (see the LED Control Register section), default: LINKUP_TXRX_ACTIVITY

LED Blink Rate

LED0_BLINK_TIME_CNTRL (see the LED 0 On/Off Blink Time Register section)

Maximum Current2

8 mA at 3.3 V

1 The 7, 8, 9, and 10 (decimal) settings in the LED0_FUNCTION bit are not available in Mode 2.

2 See Table 1 for details.

LINK STATUS PIN

Overview

The link status pin (LINK_ST/PHYAD_2) is asserted high when the

link status bit (AN_LINK_STATUS) is asserted and indicates that

the link between the ADIN1101 and its link partner is active.

The LINK_ST/PHYAD_2 pin has a weak internal pull-down resis-

tor. The pin is also used as a hardware configuration pin signal

(PHYAD_2) during power-up, hardware reset, or software reset.

Typical Use

The link status pin can be used to connect an external LED or can

be connected to a host microcontroller general-purpose input/output

(GPIO) (configured as a pulse-width modulated input or hardware

interrupt).

By default, the LINK_ST signal is active high and can be config-

ured as either active high or low using the link status polarity bit

(DGIO_LINK_ST_POLARITY). See the Pin Mux Configuration 2

The link status pin is not intended to source current. Use the circuit

recommendation in the Transistor Controlled LED section as a

reference to interface an LED on this pin. If the link status pin is

directly connected to a host controller, it is recommended to place

a low value resistance in series between the ADIN1101 link status

pin and the host controller to avoid any potential current surge. The

resistor value must be defined based on host controller capabilities.

POWER-DOWN MODES

The ADIN1101 supports the following two power-down modes:

►

Hardware power-down

►

Software power-down

Hardware power-down achieves the lowest power consumption. In

this mode, the ADIN1101 is fully turned off and the internal registers

are not accessible.

Hardware Power-Down Mode

The hardware power-down mode can be used when no operation is

required on the ADIN1101 and the power consumption needs to be

minimized.

The device enters hardware power-down mode when the RESET

pin is asserted and held low. In this mode, all analog and digital

circuits are disabled, the clocks are gated off, and all the I/O pins

are held in tristate mode.

In this mode, the ADIN1101 power consumption is equivalent to the

internal circuit leakage. The internal registers are not accessible in

this mode.

Software Power-Down Mode

The software power-down mode can be used to configure the

ADIN1101 registers before bringing a link up. In this mode, the

analog and digital circuits are in a low power state, and the PLL

is active and can provide output clocks if configured to do so. Any

signals exposed to the MDI pins (TXP, TXN, RXP, RXN) are ignored

and any active link is dropped. The MAC interface output pins are

asserted low and internal registers are accessible using the MDIO

interface.

The device can be configured to automatically enter software

power-down mode after power-up, hardware reset, or software

reset using the SWPD_EN hardware configuration pin signal. The

ADIN1101 can also be instructed to enter software power-down

mode by setting the software power-down bit (CRSM_SFT_PD).

The software power-down status bit (CRSM_SFT_PD_RDY) indi-

cates that the device is in software power-down mode.

The ADIN1101 exits software power-down mode when the

CRSM_SFT_PD bit is cleared. After exiting software power-down

and if autonegotiation is completed, the device attempts to bring a

link up.

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