ADIN1101BCPZ-R7 datasheet(73/79 Pages) AD

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Data Sheet

ADIN1101

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Rev. A | 73 of 79

Table 128. Bit Descriptions for FC_ALGN_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_ALGN_ERR_CNT

Latched Copy of the Frame Alignment Error Counter.

0x0

Frame Checker Symbol Error Count Register

Device Address: 0x1F; Register Address: 0x800D, Reset: 0x0000, Name: FC_SYMB_ERR_CNT

This register is a latched copy of the symbol error counter register. This register is a count of received frames with both RX_ER and RX_DV set.

When the receive error counter (RX_ERR_CNT) is read, the symbol error count is latched, which ensures that the symbol error count and the

frame receive count are synchronized.

Table 129. Bit Descriptions for FC_SYMB_ERR_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_SYMB_ERR_CNT

Latched Copy of the Symbol Error Counter.

0x0

Frame Checker Oversized Frame Count Register

Device Address: 0x1F; Register Address: 0x800E, Reset: 0x0000, Name: FC_OSZ_CNT

This register is a latched copy of the oversized frame error counter register. This register is a count of receiver frames with a length greater than

specified in frame checker maximum frame size (FC_MAX_FRM_SIZE). When the receive error counter (RX_ERR_CNT) is read, the oversized

frame counter register is latched, which ensures that the oversized error count and the receive frame count are synchronized.

Table 130. Bit Descriptions for FC_OSZ_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_OSZ_CNT

Latched copy of the Oversized Frame Error Counter.

0x0

Frame Checker Undersized Frame Count Register

Device Address: 0x1F; Register Address: 0x800F, Reset: 0x0000, Name: FC_USZ_CNT

This register is a latched copy of the undersized frame error counter register. This register is a count of received frames with less than 64 bytes.

When the receive error counter (RX_ERR_CNT) is read, the undersized frame error counter is latched, which ensures that the undersized

frame error count and the receive frame count are synchronized.

Table 131. Bit Descriptions for FC_USZ_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_USZ_CNT

Latched Copy of the Undersized Frame Error Counter.

0x0

Frame Checker Odd Nibble Frame Count Register

Device Address: 0x1F; Register Address: 0x8010, Reset: 0x0000, Name: FC_ODD_CNT

This register is a latched copy of the odd nibble frame register. This register is a count of received frames with an odd number of frames in the

frame. When the receive error counter (RX_ERR_CNT) is read, the odd nibble frame counter register is latched, which ensures that the odd

nibble frame count and the receive frame count are synchronized.

Table 132. Bit Descriptions for FC_ODD_CNT

Bits

Bit Name

Description

Reset

Access

[15:0]

FC_ODD_CNT

Latched Copy of the Odd Nibble Counter.

0x0

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