ADIN1101BCPZ-R7 datasheet(18/79 Pages) AD

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Data Sheet

ADIN1101

THEORY OF OPERATION

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Rev. A | 18 of 79

PHY Subsystem Reset

A PHY subsystem reset is initiated on the ADIN1101 by setting the

PHY subsystem reset register bit (CRSM_PHY_SUBSYS_RST) to

1. The reset is applied for typically 1.2 µs, and then this bit self

clears. All of the PHY digital circuitry is reset, and any available ac-

tive link drops. The PHY subsystem reset does not alter the values

of the management registers, which remain accessible throughout

the sequence. The subsystem reset is a short reset and can be

used to put the device into a known state while retaining the internal

MAC Interface Reset

A MAC interface reset is initiated on the ADIN1101 by setting the

PHY MAC interface reset register bit (CRSM_MAC_IF_RST) to 1.

The reset is applied for typically 1.2 µs, and then this bit self clears.

A reset sequence is provided to the ADIN1101 MAC interface,

but without dropping the available active link. This reset interrupts

any packet transmission or reception on the MAC interface, but

does not drop an existing active link nor prevent a link from being

established. The MAC interface reset does not alter the values of

the management registers, which remain accessible throughout the

sequence.

STATUS LEDS

Overview

The LED_0 pin can be used to connect external LEDs to indicate

the ADIN1101 link status and transmit or receive activity. The

activity assigned to each LED is configurable through LED_CNTRL

(see the LED Control Register section).

The LED_0 pin is suitable for ultra low power LEDs. The maximum

output current for the LED_0 pin is 8 mA with a VDDIO = 3.3 V. For

higher LED power requirements, the use of an external transistor

is recommended, as described in the Transistor Controlled LED

section.

The LED_0 pin can also be connected to a host microcontroller

GPIO (configured as a pulse-width modulated input or hardware

interrupt). This configuration can be useful in applications where the

user interface must be fully handled by an external host controller

(for example, an external LED module or display).

If the LED_0 pin is directly connected to a host controller, it is

recommended to place a low value resistance in series between the

ADIN1101 LED_0 pin and the host controller to avoid any potential

current surge. The resistor value must be defined based on host

controller capabilities and the ADIN1101 LED_0 pin output current

capabilities listed in Table 1.

LED Polarity

The LED_0 pin can be configured to support various LED circuit

polarities through the LED polarity mode feature (see the LED

Polarity Register section). Three polarity modes are available for

LED_0, as follows:

►

Autosense (default)

►

Active high

►

Active low

In autosense mode, the ADIN1101 automatically senses the pin at

power-up or reset to select the appropriate polarity configuration.

In active high mode, the ADIN1101 is configured to drive the LED

from the anode side.

In active low mode, the ADIN1101 is configured to drive the LED

from the cathode side.

Example circuits are described in the LED Circuit Examples sec-

tion.

LED Function

LED_0 can be configured to display various activities of the

ADIN1101 using the LED function feature. The LED function is

configurable using the LED0_FUNCTION bit (see the LED Control

The 7, 8, 9, and 10 (decimal) bit settings for LED0_FUNCTION are

not available in LED Mode 2.

LED Mode

LED_0 activity behavior can be configured using the two LED

modes, as follows:

►

LED Mode 1: blink duty cycle defined using the

LED0_BLINK_TIME_CNTRL (see the LED 0 On/Off Blink Time

►

LED Mode 2: blink duty cycle automatically defined by the

ADIN1101 based on activity level (%)

LED_0 Pin Configuration Summary

See Table 13 for the configuration options of the LED_0 pin.

Table 13. LED_0 Pin Configuration Summary

Parameter

LED_0

Pin Number

Internal Pull-Up or Pull-Down Resistor

Pull-up

Status at Power-Up or Reset

Enabled

LED Pin Mux

Not applicable

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