PM7367-PI datasheet(15/323 Pages) PMC

15 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

FEATURES

· Single-chip Peripheral Component Interconnect (PCI) Bus multi-channel

HDLC controller.

· Supports up to 32 bi-directional HDLC channels assigned to a maximum of

32 channelised T1 or E1 links. The number of time-slots assigned to an

HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for

E1).

· Supports up to 32 bi-directional HDLC channels each assigned to an

unchannelised arbitrary rate link; subject to a maximum aggregate link clock

rate of 64 MHz in each direction. Channels assigned to links 0 to 2 can have

a clock rate of up to 45 MHz when SYSCLK is at or above 25 MHz and up to

52 MHz when SYSCLK is at 33 MHz. Channels assigned to links 3 to 31 can

have a clock rate of up to 10 MHz.

· Supports up to two bi-directional HDLC channels each assigned to an

unchannelised arbitrary rate link of up to 45 MHz when SYSCLK is at or

above 25 MHz and up to 52 MHz when SYSCLK is at 33 MHz.

· Supports a mix of up to 32 channelised and unchannelised links; subject to

the constraint of a maximum of 32 channels and a maximum aggregate link

clock rate of 64 MHz in each direction.

· For each channel, the HDLC receiver performs flag sequence detection, bit

de-stuffing, and frame check sequence validation. The receiver supports the

validation of both CRC-CCITT and CRC-32 frame check sequences. The

receiver also checks for packet abort sequences, octet aligned packet length

and for minimum and maximum packet length.

· Alternatively, for each channel, the receiver supports a transparent mode

where each octet is transferred transparently to host memory. For

channelised links, the octets are aligned with the receive time-slots.

· For each channel, time-slots are selectable to be in 56 kbits/s format or 64

kbits/s clear channel format.

· For each channel, the HDLC transmitter performs flag sequence generation,

bit stuffing, and, optionally, frame check sequence generation. The

transmitter supports the generation of both CRC-CCITT and CRC-32 frame

check sequences. The transmitter also aborts packets under the direction of

the host or automatically when the channel underflows.

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