PM7367-PI datasheet(96/323 Pages) PMC

96 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

SERRE:

The system error interrupt enable bit (SERRE) enables PCI system error

interrupts to the PCI host. When SERRE is set high, any address parity error,

data parity error on Special Cycle commands, reception of a master abort or

detection of a target abort will cause an interrupt to be generated on the

PCIINTB output. Interrupts are masked when SERRE is set low. However,

the SERRI bit remains valid when interrupts are disabled and may be polled

to detect PCI system error events.

PERRE:

The parity error interrupt enable bit (PERRE) enables PCI parity error

interrupts to the PCI host. When PERRE is set high, data parity errors

detected by the FREEDM-32P32 or parity errors reported by a target will

cause an interrupt to be generated on the PCIINTB output. Interrupts are

masked when PERRE is set low. However, the PERRI bit remains valid when

interrupts are disabled and may be polled to detect PCI parity error events.

RFCSEE:

The receive frame check sequence error interrupt enable bit (RFCSEE)

enables receive FCS error interrupts to the PCI host. When RFCSEE is set

high, a mismatch between the received FCS code and the computed CRC

residue will cause an interrupt to be generated on the PCIINTB output.

Interrupts are masked when RFCSEE is set low. However, the RFCSEI bit

remains valid when interrupts are disabled and may be polled to detect

receive FCS error events.

RABRTE:

The receive abort interrupt enable bit (RABRTE) enables receive HDLC abort

interrupts to the PCI host. When RABRTE is set high, receipt of an abort

code (at least 7 contiguous 1's) will cause an interrupt to be generated on the

PCIINTB output. Interrupts are masked when RABRTE is set low. However,

the RABRTI bit remains valid when interrupts are disabled and may be polled

to detect receive abort events.

RPFEE:

The receive packet format error interrupt enable bit (RPFEE) enables receive

packet format error interrupts to the PCI host. When RPFEE is set high,

receipt of a packet that is longer than the maximum specified in the RHDL

Maximum Packet Length register, of a packet that is shorter than 32 bits

(CRC-CCITT) or 48 bits (CRC-32), or of a packet that is not octet aligned will

cause an interrupt to be generated on the PCIINTB output. Interrupts are

masked when RPFEE is set low. However, the RPFEI bit remains valid when

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